The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating fine patterns in a semiconductor device.
As semiconductor devices are highly integrated, fine patterns become necessary. However, a photolithography apparatus has a limitation to form fine space (line and space) patterns.
Recently, a double patterning method has been suggested to form patterns by using two photo masks. The double patterning method easily forms fine line and space patterns under 60 nm using a widely used photolithography apparatus. A detailed description follows referring to FIGS. 1A to 1C.
FIGS. 1A to 1C are cross-sectional views of a typical method for forming fine patterns in a semiconductor.
Referring to FIGS. 1A, a first photoresist layer PR1 is coated over an etch target layer 10. The first photoresist layer PR1 is patterned using a photo-exposure and a development process. The etch target layer 10 is etched using the patterned first photoresist layer PR1 as a mask.
Referring to FIG. 1B, after removing the patterned first photoresist layer PR1, a second photoresist layer PR2 is coated over a resultant structure and the second photoresist layer PR2 is patterned using a photo-exposure and a development process. An opening of the patterned second photoresist layer PR2 is not overlapped with that of the patterned first photoresist layer PR1.
Referring to FIG. 1C, the etch target layer 10 is re-etched using the patterned second photoresist layer PR2 as a mask. Thus, fine patterns having a narrow line and space width are formed.
However, even though the double patterning method is used, patterns having a line and space width under 30 nm are difficult to form. This result occurs because the typical method using two photo masks cannot form a line and space width under 30 nm. Further, using more than two photo masks makes it difficult to control the accuracy of an overlay during the photo-exposure process.
Thus, techniques to produce ultra fine patterns, e.g. ultra fine patterns under 20 nm, are required as semiconductor devices become highly integrated.